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W631GG6KB
CK#
CK
*5
t WLS
T1
t WLH
t WLS
T2
t WLH
Command
MRS *2
NOP *3
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
t MOD
ODT
t WLDQSEN
t DQSL *6
t DQSH *6
t DQSL *6
t DQSH *6
Diff_DQS *4
One Prime DQ:
t WLMRD
t WLO
t WLO
Prime DQ
*1
t WLO
Late Remaining DQs
Early Remaining DQs
t WLO
t WLOE
All DQs are Prime:
t WLMRD
t WLO
t WLO
Late Prime DQs *1
Early Prime DQs *1
t WLOE
t WLO
t WLOE
t WLO
UNDEFINED DRIVING MODE
TIME BREAK
DON'T CARE
Notes:
1. DRAM has the option to drive leveling feedback on a prime DQ or all DQs. If feedback is driven only on one DQ, the
remaining DQs must be driven low, as shown in above Figure, and maintained at this state through out the leveling
procedure.
2. MRS: Load MR1 to enter write leveling mode.
3. NOP: NOP or Deselect.
4. Diff_DQS is the differential data strobe (DQS, DQS#). Timing reference points are the zero crossings. DQS is shown with
solid line, DQS# is shown with dotted line.
5. CK, CK#: CK is shown with solid dark line, where as CK# is drawn with dotted line.
6. DQS, DQS# needs to fulfill minimum pulse width requirements t DQSH (min) and t DQSL (min) as defined for regular Writes; the
max pulse width is system dependent.
Figure 14 – Timing details of Write leveling sequence [DQS - DQS# is capturing CK - CK# low at
T1 and CK - CK# high at T2]
Publication Release Date: Dec. 09, 2013
Revision A05
- 32 -
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